1. Technical Field of the Invention
The present invention relates to circuits and, more particularly, to circuits including a differential amplifier with a differential transistor pair having a forward body bias.
2. Background Art
Differential amplifier circuits receive two input signals and provide output signals which are a function of a difference of the input signals. For example, the voltage difference in the output signals may be a function of the voltage difference in the input signals. In this way, the differential amplifier suppresses or rejects voltages which are included in both input signals. Examples of the suppressed voltages include a DC offset voltage and noise appearing on both input signals. This suppression is referred to as common mode rejection.
As an example, in one type of differential amplifier in the prior art, the differential amplifier includes first and second n-channel field effect transistors (nFET transistors), referred to as a differential pair. Input signals Vin+ and Vin- are received at the gates of the first and second nFET transistors, respectively. A first load is included between the drain of the first nFET transistor and a power supply. A second load is included between the drain of the second nFET transistor and the power supply. Output signals Vout+ and Vout- are at the drains of the first and second nFET transistors, respectively. The sources of the first and second nFET transistors are jointly coupled to ground through a third nFET transistor. If the first and second loads are matched and the first and second nFET transistors are matched, the difference between Vout+ and Vout- is a function of the difference between Vin+ and Vin-. Mismatches of transistor characteristics (called transistor mismatch) can reduce the accuracy of that function and ability of the amplifier to be sensitive to a small difference between Vin+ and Vin-.
In an integrated circuit, the line width Lmin is the minimum conductor width that can be accurately drawn by the lithographic equipment. For example, in much current lithographic equipment, Lmin is about 0.25 microns. The minimum will continue to get smaller for the foreseeable future.
In the process of applying conductors, there are slight variations in line width. The channel length of a transistor is related to the line width of the gate conductor, called the gate length. Variations in gate length can result in transistor mismatch. For example, referring again to the differential pair, if the channel length of the first nFET transistors is different from the channel length of the second nFET transistor, there may be mismatch between the transistors. A transistor mismatch may result in the difference between Vout+ and Vout- not accurately reflecting the difference between Vin+ and Vin-.
As the dimensions continue to get smaller, the percent difference between variations of the actual line width and the target line width is greater. Likewise, the percent difference in the actual channel length (Lactual) and target channel length (Ltarget) is greater.
One solution is too make Ltarget for the differential pair substantially larger than Lmin. For example, Ltarget may be 3 to 5 times greater than Lmin. Then, any variations in the line width will be relatively small in comparison to the actual line width and the mismatch will be relatively small. As mentioned, the channel length of a transistor is related to line width, however, there may be additional parameter variations in the actual channel length. A problem with making Ltarget much greater than Lmin is that switching speed of the transistors is inversely related to the channel length.